In conventional integrated circuits, particularly memory chips, several dies may be stacked on top of each other in a package to increase the overall capacity of the device. A ball grid array (BGA) structure is typically used for the stacked-die structure device. In such devices, a first semiconductor die is attached to the substrate via an adhesive layer. A wire bonding process is applied to electrically connect the first die to the substrate. A second die is then stacked on the first die with an adhesive layer formed between the first die and the second die. A wire bonding process is then performed to electrically connect the second die to the substrate and/or the first die. A molding compound is then formed over the substrate to encapsulate the substrate, the dies and the wires. Finally, solder balls are attached to the under surface of the substrate to contact the solder pads on the substrate. In pyramid type stacked-die applications, the first die is required to be larger than the second die.
The effectiveness of wire bonding depends on the accuracy control of die placement, selection of wire loops, wire type, capillary type and process parameters governed by the die attachment, wire bond and molding design rules. Such design rules include the control of die placement to within ±50 μm, the highest loop height to within 150 μm±25 μm, a bond line thickness to less than 75 percent of the respective die thickness, a wire angle to within ±50° and a wire sweep to less than 10 mills (254 μm). Poor settings of the process parameters and/or inappropriate wire and capillary selection may lead to a high assembly reject rate with associated problems like wire short circuits, neck ball, failed connections to the pads and/or leads, cratering of the pad and other problems.
Even with a single die device there is a problem in bonding the connections from the dies to the substrate and such problems are increased in multi-stack devices, particularly in wire bond/wire bond mode or flip-chip/wire bond mode. In particular, the molding process can detach the wires or bring them into contact with adjacent wires causing short circuits. Short circuiting may also be caused by wire strays, wire leaning and wire sweep after molding or wire bonding and can affect the performance of the device.
Conventional methods of electrically interconnecting the stacked die to the substrate have a number of defects. In particular, conventional methods may suffer from one or more of the following problems, such as wire shorting due to die placement offset, inappropriate wire and capillary use, wrong parameter settings (wire loops), mishandling of bonded strips, excessive wire sweep after molding, non-stick-on pad due to the wrong parameter setting (USG current), contamination of the bond pad, large probe mark size and wrong bonding.
Furthermore, wire leaning and/or wire sways immediately after wire bonding could affect the performance of molding with the high possibility of wire shorting as a result. In addition, inappropriate loop length and height of the loops, as well as weak interconnect adhesion could all further aggravate the encapsulation process. Also, a capillary touching a wire and a wire touching the die edge could both result in poor bonding performance, which affects the operation of the device.
In view of the foregoing problems with conventional processes and devices, a need exists for a quick and an easily applied method for connecting dies and substrates.